Sr. Digital Verification Engineer

The Allegro team is passionate about providing intelligent solutions that move the world toward a safer and more sustainable future.With more than 30 years of experience developing advanced semiconductor technology, innovation with purpose touches every aspect of our business. From customer engagement and employee recognition to technology advancement and serving the local communities in which we maintain offices, innovation consistently drives our mission and definition of success.As part of our innovation, we recognize that our team members are unique and that our work locations must be adaptable. At Allegro weflex & adaptis our approach to hybrid work that empowers managers and their team members to decide where and when work will be done. Ask what it can mean for you.WHAT YOU WILL DO:Preparation of digital design test plan from requirements using Cadence-vManager/vPlannerDefinition and creation of UVM-SV test environment, test plans, tests and functional coverageVerification of signal processing and control algorithms using Cadence and MathWorks toolsAnalysis of test results, improving test coverage and debug of unexpected design behaviorRunning and maintenance of regression runsPreparation and/or leading of verification reviewsModification and/or debug of Simulink models in mixed signal test environmentCoordination of verification activities with abroad team membersCooperation with System Engineering team on Jama RequirementsQUALIFICATIONS:The successful candidate will possess a Bachelor's / Master's degree of 5+ / 3+ years of experience in Digital Design and/or Verification. Excellent communication, documentation, problem-solving and analytical skills are required. Knowledge of SystemVerilog and UVM is a must. Experience with the usage of Jama, MATLAB/Simulink, Python is a strong plus.#J-18808-Ljbffr