Mixed Signal Design Verification Engineer

Key QualificationsHands on experience in mixed signal verificationAnalog and digital design background that supports the analysis of verification resultsExperience in behavioral modelling using System Verilog and Verilog AMS, targeting analog, digital or mixed signal verification environmentsKnowledge of UVM, Assertion Based Verification, Formal Verification techniques is considered a plusKnowledge of scripting languages (Python/Perl/TCL)Outstanding sense and aim for quality of work you're doingTeammate with excellent written and verbal communication skillsAlways enthusiastic to collaborate with diverse teams and take on diverse challenges with international teamsDescriptionYou will work within the Analog Mixed Signal Design Verification Team with experienced Verification Engineers, in order to achieve top-level mixed signal verification with the highest quality, efficiency, and time-to-market.
You will collaboratewith the architecture, analog, digital, and software teams to ensure specification compliance and accurate functionality, and to guarantee that potential issues are taken care of as early as possible in the design cycle.
You will develop verification test plans, behavioral models, high-coverage stimulus vectors, tools, test benches, monitors and checkers in analog, digital and mixed signal verification environments.