Description :Astreya is a leading IT solutions provider to deliver technology-enabled services and fuel digital transformation to some of the most exciting companies on the planet.
We are working with the world's most recognizable and innovative organizations through co-creating scalable solutions with fast-moving teams.
Here you will have the creative autonomy to build new capabilities for next generation hardware architectures.
You will get exposure to a wide variety of new tools and technologies to improve ASIC design verification.
By joining the verification engineering team you will witness advances in continuous technical innovation and showcase the team's successes as well as facilitate continuous career development.Key Responsibilities: Collaborate with design engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, with focus on use cases described in the architecture and design specificationsDrive the testbench architecture and development of leading edge IPDevelop directed and constrained random test scenarios as identified in the test planEstimate the time required to write the new feature tests and any required changes to the test environment Debug test failures to determine the root cause; work with RTL engineers to resolve design defects and correct any test issues?Review functional and code coverage metrics – modify or add tests or constraint random tests to meet the coverage requirementsPush for adoption of best practices in the industryEvaluate tools for improving performance and reduce the development cyclePropose innovative ways to architect reusable test benchesOffer mentorship to junior engineers?Qualifications / Experience: Proficient in IP level ASIC verification Extensive experience in designing and implementing self-checking test benches, coverage closure techniques and regression management flowsProficient in debugging RTL code using simulation tools Proficient working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Hands-on experience with UVM based verification frameworks and testbenches, processes and flows Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Experience and knowledge of communications standards (such as Ethernet, Flex Ethernet, OTN, Interlaken)Experience and knowledge with IEEE security protocols (such as MACsec, IPsec)Good working knowledge of SystemC and TLM with some related experience.
Scripting language experience: Perl, Ruby, Makefile, shell preferred.
Exposure to leadership or mentorship opportunitiesBachelors or Masters degree in computer engineering/Electrical Engineering/computer systems/computer scienceStrong team player with excellent communication skills and experience collaborating with other engineers located in different sites/timezones.Expert level analytical and problem-solving skills with a willingness to learn and the capability to take on complex problems.Physical Demand & Work Environment:Must have the ability to perform office-related tasks which may include prolonged sitting or standingMust have the ability to move from place to place within an office environmentMust be able to use a computerMust have the ability to communicate effectively Some positions may require occasional repetitive motion or movements of the wrists, hands, and/or fingers
