Digital Ic Verification Engineer

Working for a leader in power electronics, this is a great opportunity to join a growing team as a UVM Verification Engineer.
Job Duties: Developing test plans, tests, and verification infrastructure using SV/UVM methodology Building reusable bus functional models, monitors, checkers, and scoreboards Performing coverage driven verification closure Performing block level, multi-block level, and system-level verification Performing gate level simulations Performing mixed signal simulations Implementing regression tests Performing formal verification Working closely with IC designers and post-silicon engineers Qualifications and Background Requirements: Knowledge/experience with HDL (SystemVerilog / Verilog / VHDL), particularly for testbench creation Knowledge/experience in scripting languages, such as Tcl and Python Some knowledge of ASIC design flow and related verification steps Nice to Have: Some experience in digital RTL design Knowledge of UVM environments and classes Some experience with main EDA vendors simulators such as Questasim and Xcelium Knowledge of DFT structures and test pattern generation Some experience in silicon validation/characterization Experience working on Git For more information, please contact Rob Hudson.
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