To strengthen their existing IC design team, my client are currently looking for a junior digital IC designer. The engineer requested for this position will be responsible for design, simulation and full validation of several programmable functional units within a complex IC device, which is at the core of their flagship power adapter product. you will be reporting to the head of the IC team. The selected person will work in close collaboration with our R&D team for the development of new IPs to be integrated into the next generation ASICs.Main Responsibilities:You should be a motivated and proactive engineer, able to work well within an independent team and ready to be involved in:VHDL / Verilog / System-Verilog design at RT-Level of core functional blocksImplementation of RTL-to-Syn IC design flow, including timing/power analysisVerification of digital IPs using simulation tools at different abstraction level (from RTL to post-layout)Co-simulation of digital and analog IPs to validate the whole mixed-signal systemFPGA prototyping of core digital IPsSilicon validation activities with laboratory instrumentationJob OverviewTo strengthen their existing IC design team, my client are currently looking for a junior digital IC designer. The engineer requested for this position will be responsible for design, simulation and full validation of several programmable functional units within a complex IC device, which is at the core of their flagship power adapter product. you will be reporting to the head of the IC team. The selected person will work in close collaboration with our R&D team for the development of new IPs to be integrated into the next generation ASICs.Main Responsibilities:You should be a motivated and proactive engineer, able to work well within an independent team and ready to be involved in:VHDL / Verilog / System-Verilog design at RT-Level of core functional blocksImplementation of RTL-to-Syn IC design flow, including timing/power analysisTestbench design in system-verilog (UVM compliant)Verification of digital IPs using simulation tools at different abstraction level (from RTL to post-layout)Co-simulation of digital and analog IPs to validate the whole mixed-signal systemFPGA prototyping of core digital IPsSilicon validation activities with laboratory instrumentationQualifications and BackgroundPhD or MS Degree in Microelectronics or Physics3-10+ years related experienceStrong knowledge of the CMOS technology, standard logic libraries and manufacturing processGood knowledge of VHDL or Verilog or System-Verilog languageBasic knowledge of programming and scripting languages like C++, TCL, bash, PerlGood experience of translating design requirements into RTL descriptionExperience of digital or mixed-signal verification activities, testbench and verification planning, regression testsConsolidated knowledge on complete ASIC design flow (from RTL to GDSII)Good knowledge of existing EDA tools (Cadence or Synopsys Design Framework)Good English knowledge (written and spoken)Nice to haveBasic knowledge of some modelling languages like Verilog-A or VHDL-AMSGood knowledge of microprocessor design (architecture, definition of a custom ISA, implementation data/memory bus)#J-18808-Ljbffr
