General description and main responsibilities CORTUS is working on the next generation of IoT connectivity modems building up 5G massive Machine Type Communication (mMTC) chipset that will define ultra low power, high reliability and low cost benchmarks for SoC products. To become a chip leader in wireless connectivity for the IoT market, we are looking for Mid / Senior Digital Verification Engineers (m / f) for our R&D centers of excellence. The candidate must have a background in digital electronic design with at least 5 years of experience in design and verification languages (Verilog, SystemVerilog), methodologies (Formal, UVM) and well knowledgeable of the entire VLSI flow. The candidate will be well versed with verification methodology and create verification plans as well as test bench architecture to run digital and top level simulations using state of the art EDA tools. He / She will directly interact with system architects, Digital design team, AMS design teams to lead the verification flows of the CORTUS' SoC family product for wireless connectivity. The ideal applicants should be familiar with working in a multicultural environment and with teams spread over several sites. Engineering Msc. or Bsc. degree in Electronics / Telecommunications / Computer Science or equivalent; Good understanding of the standards NB IoT, BLE and IEEE 802.15.4; Deep experience in defining IPs test specification in closed collaboration with product definers and architects; Strong experience on digital verification methodologies (Formal and UVM) using state of the art EDA tools; Understand and debug digital RTL; Determine technology requirements, dependencies and deliverables based on project specifications; Experience in writing IP verification plans, creating test benches and automating regression test suites to ensure 100% coverage prior to tape out; Experience with mixed signal (analog, digital) verification methodologies using state of the art EDA tools; Capability in developing behavioral models for analog IPs, understand and debug analog schematics; Knowledge of Design For Testability (DFT) techniques; Scheduling and reporting activities; English language written and spoken; Proven communication / interpersonal skills; Able to assume responsibility for a variety of technical tasks and troubleshooting; Strong sense of responsibility and ability to achieve deadlines. Highly preferred skills (plus) Basic Experience with RISK V ISA; Basic Experience in Digital Signal Processing (DSP); Script programming language (e.g. perl, shell, python); Familiar with real time embedded software (especially debugging). Job type and primary locations Full time with permanent contract Primary locations : LECCE, (Apulia region), Italy J-18808-Ljbffr