General description and main responsibilities Cortus is working on next generation IoT connectivity modems building up 5G massive Machine Type Communication (mMTC) chipset that will define ultra–low power, high reliability and low–cost benchmarks for SoC products that rely on NB–IoT, BLE and IEEE 802.15.4.
To become a chip leader in wireless connectivity for the IoT market, we are looking for Mid/Senior Radio Frequency Design Engineers to strengthen our on–site team.
The candidate must have a solid background in RF microelectronics with at least 3+ years of experience in Radio Frequency IC design.
As a Radio Frequency IC designer, the candidate will specify, design, layout and test Radio frequency (e.g.
PA, LNA/LNTA, mixer, HF oscillators, LO driver, VGA and TIA blocks in deep sub–micron CMOS technology) directly interacting with system architects, Digital design team, AMS design teams and test engineers for the integration of the RF functions into the CORTUs' SoC family product for wireless connectivity.
The ideal applicants should be familiar with working in a multicultural environment and with teams spread over several sites.
Minimum requirements Engineering MSc.
or BSc.
degree in Electronics/Telecommunications or equivalent; Direct tape–out experience in design and test of one or more of the following RF blocks: PA, LNA, mixer, HF oscillators, LO driver, VGA and TIA; Experience in Power Management architecture typologies, such as PWM control, constant–on–time control, and voltage/current mode controls; Capability to handle the design of CMOS/BCD power management circuits (buck, boost, LDOs, bandgaps, bias, comparators, and op–amps) with main EDA tools and meeting performance, area, power and speed constraints; Capability to review and provide feedback for Printed Circuit Board design from a power perspective and associated I/O; Knowledge of physical construction and characteristics of capacitors and inductors (on–chip and off–chip); Knowledge of Latch–Up and ESD phenomena to assure the functional security of the system; English language written and spoken.
Highly preferred skills (plus) Good understanding of the standards NB–IoT, BLE and IEEE 802.15.4; Deep experience in translating schematics to mask layouts; Experience with all aspects of physical ASIC/SoC integration including floorplanning, clock and power distribution, global signal planning, I/O planning and hard IP integration; Experience with layout implementation criticalities (e.g.
matching, electro–migration, Latch–Up and ESD); Capability to handle main Physical Design Verification flow steps performing LVS, DRC, ERC, and all required verifications with corresponding main EDA tools; Capability to handle top–level layout integration tape–out process, which involves generation of bond diagram/RDL, final clean GDS database and proper documentation; Knowledge about Analog–On–Top and Digital–On–Top approach and methodologies, PR flow steps; Scheduling and reporting activities; Proven communication/interpersonal skills; Able to assume responsibility for a variety of technical tasks and troubleshooting; Strong sense of responsibility and ability to achieve deadlines.
Job type, primary locations and application reference Full time with permanent contract Primary locations: LECCE, (Apulia region), Italy #J-18808-Ljbffr
